In the course of manufacturing semiconductor integrated circuits (IC), dry etching techniques, including plasma reactive ion etching (RIE), are extensively used for the removal or the patterning of layers of various materials, particularly of layers of dielectric material formed on the substrate. During the removal of such layers or films, pinpointing with accuracy the etch end point to stop etching at a given thickness is of paramount importance for process parameter control and for determining the characteristics and performance of the resulting IC. As a matter of fact, it is essential that the remaining thickness of a dielectric layer be equal or very close to the nominal value established in the product specifications. In addition, this remaining thickness must be maintained at constant from wafer to wafer. Obtaining such thickness with adequate reproducibility is a key factor to a successful completion of the processing steps to which the wafers are subsequently subjected to.
FIG. 1 is a schematic view of a portion of a wafer which consists of a semiconductor structure 10, and which essentially comprises a silicon substrate 11 and a stack 12 of insulating layers formed thereon. Typically, the stack 12 consists of a lower 30 nm thick SiO.sub.2 layer 13, an intermediate 150 nm thick Si.sub.3 N.sub.4 layer 14 and an upper SiO.sub.2 layer 15. The interface between the lower SiO.sub.2 layer 15 and the top of Si.sub.3 N.sub.4 layer 14 is labelled 16a. The top surface of the SiO.sub.2 layer 15 is referenced 16b. Layer 15 is generally formed by LPCVD (Low Pressure Chemical Vapor Deposition)/PECVD (Plasma Enhanced Chemical Vapor Deposition) using tetra-ethyl-ortho-silicate (TEOS) and oxygen. The substrate is provided with a shallow isolation trench 17. As such, structure 10 is a typical example of a silicon wafer after an isolation trench is formed during the fabrication of a 16 Mbit DRAM chip. At this stage, the structure 10 is planarized and the initial thickness E of the SiO.sub.2 layer 15 is reduced to a predetermined value Ef, commonly defined in the product specifications. To that end, the structure 10 is coated with a layer 18 of a planarizing medium, such as a photo-resist, having broadly the same etch rate as the SiO.sub.2 material. The structure 10 is etched back inside the chamber of a conventional dry etching tool. This etch back is generally completed in two processing steps, each having its own gas chemistry. During the first step of the etch back process, the structure 10 is etched until the top of the SiO.sub.2 layer 15 is exposed. In the second step, which uses a more reactive gas chemistry for greater aggressiveness, the SiO.sub.2 layer 15 is etched from surface 16b to a depth equal to Exf=E-Ef. The planar top surface of the remaining SiO.sub.2 layer 15 after etching is referenced with numeral 16c.
FIG. 1 shows a typical structure fabricated in a manufacturing environment. It generally consists of a substrate (that includes a silicon substrate 11 upon which a layer of SiO.sub.2 13 and a layer of Si.sub.3 N.sub.4 14 are formed thereon) coated with a dielectric layer (SiO.sub.2 layer 15). It requires two different optical media at the interface 16a to allow interferometric measurements and to etch the dielectric layer down to a given thickness using a dry etching tool.
The etch back process may be monitored in its totality using the well known time thickness control technique which is based on the assumption that the etch rate of the SiO.sub.2 layer 15 is constant and can be determined before the etch back step of the wafer takes place. The etch rate value is determined either from the teachings obtained from the processing of a previous lot on the same tool or by processing a sample wafer of the lot under consideration inside the tool and then determining the etch rate value from this experiment. The latter is more accurate but it is time consuming and may lead to wasting an expensive wafer for each lot, such as in the case of over-etching, which is not acceptable in a manufacturing environment. According to the time monitoring technique, the etching process is stopped as soon as the final etched thickness Exf is attained. The real thickness Eyf of the remaining SiO.sub.2 layer 15 is finally measured according to standard spectroscopic interferometry techniques and compared to the desired final thickness Ef. If the SiO.sub.2 layer 15 is found to be over-etched, the wafer is rejected since no adjustment is possible. If the thickness Eyf is above the desired final thickness value Ef, the wafer is submitted to a new etching step in order to come closer to the desired thickness Ef. In this case, an additional etch-back and corresponding measurements are required as well.
Another well known monitoring technique is based on interferometry. This technique allows in-situ, real-time, and on-line control of the current etched thickness Ex (the current thickness of the remaining SiO.sub.2 layer 15 is referenced Ey, wherein as Ey=E-Ex). During the etch back process previously mentioned, once the top of the SiO.sub.2 layer 15 is exposed, the etch rate and the current etched thickness Ex can be continuously and accurately monitored. According to the standard technique, a monochromatic radiation emitted by a laser impinges the wafer incorporating the structure 10 at a normal angle of incidence. Interference fringes are formed by the radiations refracted from the top of SiO.sub.2 layer 15 and at the interface 16a formed between SiO.sub.2 layer 15 and the underlying layer 14 of Si.sub.3 N.sub.4. An adequate detector, generally a photo-diode is illuminated by the reflected radiations and generates a signal whose intensity varies with the thickness of SiO.sub.2 layer 15 to be etched. An improvement of this technique is described in European Patent No. A-0511448, of common assignee. According to this reference, a laser is no longer required, a determined radiation emitted by the plasma (in this case, the SiBr line) is observed through a top view-port by a spectrometer operating as an interferometer and through a side view-port by a second spectrometer. The signals generated by these spectrometers are processed by computer according to the claimed method described therein. This technique requires radiation of sufficient intensity to be observed The etching process stops when Ex=Exf. The thickness of the remaining SiO.sub.2 layer is thus given by Eyf=E-Exf. The true thickness Eyf of the remaining SiO.sub.2 layer cannot be measured on-line and in-situ with this technique, but needs to be performed outside the dry etching tool. In addition, the plasma is a very unstable medium whose parameters can only be determined by process requirements (and thus not for monitoring), the selected radiation of a determined wavelength may reveal itself not to be optimal. Finally, the plasma is not a pin-point source. As a final result, this improved method still suffers from severe limitations.
The insulating layers cited above, particularly the SiO.sub.2 layer 15 that was formed by LPCVD techniques, are known to have low reproducibility. As a result, the thickness of the deposited SiO2 layer 15 and the composition of the deposited material may significantly vary from wafer to wafer. Consequently, the thickness of the SiO.sub.2 layer 15 is no longer given by its theoretical value E but must be approximated by a value equal to E.+-.e, wherein e represents the admitted error on the thickness due to process variations during the LPCVD deposition. Typically, e is equal to about 10% of the initial thickness of the SiO.sub.2 layer 15. Thus, if Exf is the final etched thickness, the final thickness of the remaining SiO.sub.2 layer is given by Eyf=(E.+-.e)-Exf. This value Eyf may differ from the desired thickness value Ef. Alternatively, the error.+-.e relative to the original thickness E of the SiO.sub.2 layer 15 is reported to the real final thickness, i.e., Eyf=Ef.+-.e. The interferometric method thus provides an accurate and continuous measurement of etched thickness Ex (stop etching when a determined thickness Exf has been removed). Unfortunately, this is not the current thickness Ey of the SiO.sub.2 layer 15 which remains on the substrate and, thus, the true final thickness Eyf at the end of the etch back operation. This results in a lack of compensation of the thickness error.+-.e, since the true final thickness Eyf of the remaining SiO2 layer 15 that is obtained at the end of the etch process is not directly available in real time for comparison with the thickness Ef.
These considerations will be better understood by reference to FIG. 2(a) which shows a sine wave curve labelled 19a that is theoretically generated by the photo-diode of the spectrometer. In reality, due to the presence of harmonics in the signal outputted by the spectrometer, the signal is periodic but it is not sine wave shaped. In the case of normal incidence, two successive extrema (minima to maxima or conversely) which correspond to a half-period are separated by a distance d according to the relation d=L/4*N, wherein L is the wavelength and N the refraction index of the SiO.sub.2 layer 15. In turn, the etch rate ER and the etched thickness during the half-period is correlated by the equation ER=2*d/T, wherein T is the period of the periodic signal. Because of the thickness error e due to the process variations mentioned above, the current thickness Ey will depend on the real thickness value of the SiO.sub.2 layer 15 (i.e., E.+-.e), as illustrated in FIG. 2(a). Curve 19a passes through a maximum at interface 16a. Process variations thus lead to an error while determining Ey which results in stopping the etching process at a final thickness value Eyf of the remaining SiO.sub.2 layer 15 which may be significantly different from the desired thickness Ef.
Additionally, differences in composition exist in the deposited materials forming the various layers of stack 12 mentioned above with respect to the expected compositions. In particular, this results in slight differences in the nominal refraction index N of the SiO.sub.2 layer 15 and, more generally, of the refraction index of all the other layers forming stack 12. Moreover, other layers may also have a variable thickness with regard to their respective nominal thickness, producing significant topographical differences. Finally, differences between product wafers within a lot are a major source of concern. These differences generally result from process variations that are inherent to any semiconductor devices manufacturing technology. The sine wave curve 19a of FIG. 2(a) is illustrative of a perfect adaptation of a wavelength L of the monochromatic radiation with the nominal refractive index N of the SiO.sub.2 layer 15 and, more generally, of the optical characteristics of stack 12. As far as the structure 10 of FIG. 1 is concerned, the true value of the refractive index is given by N.+-.n, with N=1.48 and the error n=0.002, i.e., the true value of N varying between about 1.46 and about 1.50. As soon as a discrepancy occurs between the selected wavelength and the refractive index, a degradation in the signal outputted by the spectrometer ensues, as illustrated by curve 19b of FIG. 2(b). In this case, monitoring the dry etch process to detect the etch end point is no longer possible.
The typical value of the thickness E of SiO.sub.2 layer 15 is thus equal to 650.+-.65 nm. This value is compared with the desired thickness of the layer 15 remaining after the planarization step, given in this instance by Ef=100.+-.5 nm. As a result, the error e=65 nm related to the nominal thickness E=650 nm of the SiO.sub.2 layer 15 is related to the thickness of the remaining SiO.sub.2 layer 15 in its totality, while the thickness error on the remaining SiO.sub.2 layer 15 that is sought should be equal to or be less than 5 nm. It is important that the thickness error e=65 nm be of the same order of magnitude than the thickness Ef=100 nm of the remaining SiO.sub.2 layer 15. A major problem is thus to eliminate the thickness error e and the refraction index error n.